may 2003 copyright ? alliance semiconductor. all rights reserved. ? as7c1025a as7c31025a 5v/3.3v 128k x 8 cmos sram (revolutionary pinout) 5/28/03; v.0.9.9 alliance semiconductor p. 1 of 8 features ? as7c1025a (5v version) as7c31025a (3.3v version) industrial and commercial temperatures organization: 131,072 x 8 bits high speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time low power consumption: active - 853 mw (as7c1025a) / max @ 10 ns (5v) - 522 mw (as7c31025a) / max @ 10 ns (3.3v) low power consumption: standby - 55 mw (as7c1025a) / max cmos (5v) - 36 mw (as7c31025a) / max cmos (3.3v) latest 6t 0.25u cmos technology easy memory expansion with ce , oe inputs center power and ground ttl/lvttl-compatible, three-state i/o jedec-standard packages - 32-pin, 300 mil soj - 32-pin, 400 mil soj - 32-pin, tsop 2 esd protection 2000 volts latch-up current 200 ma logic block diagram 512 256 8 array (1,048,576) sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce we column decoder row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a12 a11 a10 a9 a8 a0 a1 a2 a3 ce i/o0 i/o1 v cc gnd i/o2 i/o3 we a4 a5 a6 a7 as7c1025a as7c31025a 32-pin soj (300 mil) 32-pin soj (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 v cc gnd i/o2 i/o3 we a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a9 a8 a4 a5 a6 a7 a12 a11 a10 32-pin tsop 2 as7c1025a as7c31025a selection guide -10 -12 -15 -20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5 6 7 8 ns maximum operating current as7c1025a 155 150 145 140 ma as7c31025a 145 140 135 130 ma maximum cmos standby current as7c1025a 10 10 10 10 ma as7c31025a 5 5 5 5 ma
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 2 of 8 ? functional description the as7c1025a and as7c31025a are high-performance cmos 1,048,576-bit st atic random access memory (sram) devices organized as 131,072 x 8 bits. they are designed for memory applications where fa st data access, low power, an d simple interfacing are desir ed. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with outp ut enable access times (t oe ) of 5, 6, 7, 8 ns are ideal for high-performance applications. the chip enable input ce permits easy memory and expansion with multiple-bank memory systems. when ce is high the devices enter standby mode. the standard as7c1025a is guaranteed not to exceed 55 mw power consumption in standby mode. a write cycle is accomplished by asserting write enable ( we ) and chip enable ( ce ). data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devi ces should drive i/o pins only after outputs have been disabled with
oe
( we ). a read cycle is accomplished by asserting output enable ( oe ) and chip enable ( ce ), with write enable ( we ) high. the chips drive i/o pins with the data word referenced by the input address. when either ch ip enable or output enable is inactive, or write enable is ac tive, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compat ible, and operation is from a single 5v supply (as7c1025a) or 3.3v supply (as7c31025a ). the as7c1025a and as7c31025a are packaged in common industry standard packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions outside th ose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. key: x = don?t care, l = low, h = high absolute maximum ratings parameter device symbol min max unit vo l t ag e o n v cc relative to gnd as7c1025a v t1 ?0.50 +7.0 v as7c31025a v t1 ?0.50 +5.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc + 0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 o c ambient temperature with v cc applied t bias ?55 +125 o c dc current into outputs (low) i out ?20ma truth table ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 3 of 8 ? ? v il min. = ?3.0v for pulse width less than t rc /2. recommended operating conditions parameter device symbol min nominal max unit supply voltage as7c1025a v cc 4.5 5.0 5.5 v as7c31025a v cc 3.0 3.3 3.6 v input voltage as7c1025a v ih 2.2 ? v cc + 0.5 v as7c31025a v ih 2.2 ? v cc + 0.5 v both v il ? ?0.5 ? 0.8 v ambient operating temperature commercial t a 0?70 o c industrial t a ?40 ? 85 o c dc operating characteristics (over the operating range) parameter sym test conditions device -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc both ? 1 ? 1 ? 1 ? 1 a output leakage current | i lo | v cc = max, ce = v ih , v out = gnd to v cc both ? 1 ? 1 ? 1 ? 1 a operating power supply current i cc ce = v il , f = f max, i out = 0 ma as7c1025a ? 155 ? 150 ? 145 ? 140 ma as7c31025a ? 145 ? 140 ? 135 ? 130 standby power supply current i sb ce = v ih , f = f max , f out = 0 as7c1025a ? 30 ? 25 ? 20 ? 20 ma as7c31025a ? 30 ? 25 ? 20 ? 20 i sb1 ce v cc ?0.2v, v in 0.2v or v in v cc ?0.2v, f = 0, f out = 0 as7c1025a ? 10 10 10 10 ma as7c31025a ? 5555 output voltage v ol i ol = 8 ma, v cc = min both ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 2.4 ? 2.4 ? 2.4 ? v capacitance ( f = 1 mhz, t a = 25 o c, v cc = nominal ) parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 4 of 8 ? key to switching waveforms read waveform 1 (address controlled) read waveform 2 (ce and oe controlled) read cycle (over the operating range) parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10 ? 12 ? 15 ? 20 ? ns address access time t aa ? 10 ? 12 ? 15 ? 20 ns 3 chip enable (ce ) access time t ace ? 10 ? 12 ? 15 ? 20 ns 3 output enable (oe ) access time t oe ?5? 6?7 ? 8 ns output hold from address change t oh 2 ? 3 ? 3 ? 3 ? ns 5 ce low o output in low z t clz 0 ? 0 ? 0 ? 0 ? ns 4, 5 ce high to output in high z t chz ? 5 ? 6 ? 7 ? 7 ns 4, 5 oe low to output in low z t olz 0 ? 0 ? 0 ? 0 ? ns 4, 5 oe high to output in high z t ohz ? 5 ? 6 ? 7 ? 7 ns 4, 5 power up time t pu 0 ? 0 ? 0 ? 0 ? ns 4, 5 power down time t pd ? 10 ? 12 ? 15 ? 20 ns 4, 5 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% data valid t rc1 ce t ohz
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 5 of 8 ? write waveform 1 (we controlled) write cycle (over the operating range) parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 ? 12 ? 15 ? 20 ? ns chip enable (ce ) to write end t cw 8 ? 10 ? 12 ? 12 ? ns address setup to write end t aw 8?9 ?10?12? ns address setup time t as 0?0 ? 0? 0 ? ns write pulse width t wp 7?8 ? 9?12? ns write recovery time t wr 0?0 ? 0? 0 ? ns address hold from end of write t ah 0?0 ? 0? 0 ? ns data valid to write end t dw 5?6 ? 8?10? ns data hold time t dh 0 ? 0 ? 0 ? 0 ? ns 4, 5 write enable to output in high z t wz ? 6 ? 6 ? 6 ? 8 ns 4, 5 output active from write end t ow 1 ? 1 ? 1 ? 2 ? ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 6 of 8 ? write waveform 2 (ce controlled) ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, and c. 4t clz and t chz are specified with cl = 5pf, as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not 100% tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during addr ess transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 na. 13 c=30pf, except all high z and low z parameters, where c=5pf. t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr 255 ? ? output load: see figure b or figure c. ? input pulse level: gnd to 3.0v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5v. c(14) 320 ? d out gnd +3.3v 168 ? thevenin equivalent: d out +1.728v (5v and 3.3v) figure c: 3.3v output load 255 ? c(14) 480 ? d out gnd +5v figure b: 5v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
as7c1025a as7c31025a 5/28/03; v.0.9.9 alliance semiconductor p. 7 of 8 ? package dimensions symbol 32-pin tsop 2 (mm) min max a ?1.2 a1 0.05 0.15 b 0.3 0.52 c 0.12 0.21 d 20.82 21.08 e1 10.03 10.29 e 11.56 11.96 e 1.27 bsc l 0.40 0.60 zd 0.95 ref. 0 5 32-pin tsop 2 nn/2+1 1n/2 d e1 e l c zd c b a1 a seating plane e d e1 pin 1 b b a1 a2 c e seating plane e2 a 32-pin soj 300 mil/400 mil symbol 32-pin soj 300 mil 32-pin soj 400 mil min max min max a -0.145-0.145 a1 0.025 - 0.025 - a2 0.086 0.105 0.086 0.115 b 0.026 0.032 0.026 0.032 b 0.014 0.020 0.015 0.020 c 0.006 0.013 0.007 0.013 d 0.820 0.830 0.820 0.830 e 0.250 0.275 0.360 0.380 e1 0.292 0.305 0.395 0.405 e2 0.330 0.340 0.435 0.445 e 0.050 bsc 0.050 bsc
as7c1025a as7c31025a ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and p roduct names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/o r estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant chan ges to these specifications are possible. the information in this p roduct data sheet is intended to be general descriptive information for potential customers and users, and is not intended to o perate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product describ ed herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchan tability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manu facturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. 5/28/03; v.0.9.9 alliance semiconductor p. 8 of 8 ? ordering codes package \ access time vo l t . temperature 10 ns 12 ns 15 ns 20 ns tsop 2 5v commercial as7c1025a-10hfc as7c1025a- 12hfc as7c1025a-15hfc as7c1025a-20hfc industrial as7c1025a-10ti as7c1025a- 12hfi as7c1025a-15hfi as7c1025a-20hfi 3.3v commercial as7c31025a-10hfc as7c31025a- 12hfc as7c31025a-15hfc as7c31025a-20hfc industrial as7c31025a-10hfi as7c31025a-12hfi as7c31025a-15hfi as7c31025a-20hfi 300-mil soj 5v commercial as7c1025a-10t jc as7c1025a-12tjc as7c1025a-15tjc as7c1025a-20tjc industrial as7c1025a-10tji as7c1025a-1 2tji as7c1025a-15tji as7c1025a-20tji 3.3v commercial as7c31025a-10tjc as7c31025a- 12tjc as7c31025a-15tjc as7c31025a-20tjc industrial AS7C31025A-10TJI as7c31025a- 12tji as7c31025a-15tji as7c31025a-20tji 400-mil soj 5v commercial as7c1025a-10jc as7c1025a -12jc as7c1025a-15jc as7c1025a-20jc industrial as7c1025a-10ji as7c1025a- 12ji as7c1025a-15ji as7c1025a-20ji 3.3v commercial as7c31025a-10jc as7c31025a -12jc as7c31025a-15jc as7c31025a-20jc industrial as7c31025a-10ji as7c31025a- 12ji as7c31025a-15ji as7c31025a-20ji part numbering system as7c x 1025 ?xx x x sram prefix vo l t ag e : blank=5v cmos 3=3.3v cmos device number access time package: hf = tsop 2 / 32 pin tj = soj 300 mil j = soj 400 mil temperature range c = commercial, 0c to 70c i = industrial, -40c to 85c
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